In the initial stage of the development of semiconductor device fabricating technology, germanium Ge was the most desirable semiconductor material. However, from the early 1960s, germanium Ge started to be rapidly replaced by silicon Si, and Si has become material that takes lead in semiconductor integrated circuit technology.
With regard to the CMOS process using Si, an n-well process in which an n-MOSFET is implemented in a p-type silicon substrate and an n-well is formed to implement a p-MOSFET is used, a p-well process in which a p-well is formed in an n-type silicon substrate, and a twin-well process in which both an n-well and a p-well are formed in a substrate doped at a low concentration. Using the twin-well process, the performances of a p-MOSFET and an n-MOSFET can be optimized, and the reliability problem of a substrate region having a low dopant concentration, called latch-up, can be overcome.
Generally, a CMOS transistor is configured such that an n-channel MOS transistor and a p-channel MOS transistor are connected to each other and operate in conjunction with each other. A conventional method of fabricating a CMOS transistor is described below.
First, an isolation layer is formed on a silicon substrate, i.e., a semiconductor substrate, using a LOCal Oxidation of Silicon (LOCOS) or Shallow Trench Isolation (STI) process. Furthermore, an n-well is formed by injecting phosphorus P, i.e., n-type dopant, into the semiconductor substrate through a low-concentration ion injection process, and a p-well is formed by ion-injecting boron B, i.e., p-type dopant, into an adjacent portion of the semiconductor substrate.
A gate insulation film is deposited above the n-well and p-well of the semiconductor substrate, poly-silicon is deposited on the gate insulation film as conductive material, and these are patterned by a dry etching process using a gate mask. Accordingly, the gate insulation film and a gate electrode are stacked above the n-well, and the gate insulation film and a gate electrode are stacked above the p-well.
Thereafter, an LDD ion injection process is performed on each of the wells using the gate electrode as a mask, and a silicon nitride layer is deposited on all the surfaces of the substrate as insulating material and then dry-etched, thereby forming a spacer on a side surface of the gate electrode of the n-well and a spacer on a side surface of the gate electrode of the p-well.
Thereafter, a source/drain ion injection process is performed on each of the wells using the gate electrode and the spacer as a mask, and thus a p+-type source/drain junction layer into which high-concentration p-type dopant has been injected is formed inside the n-well and an n+-type source/drain junction layer into which high-concentration n-type dopant has been injected is formed inside the p-well. The CMOS process is completed by performing a metallization process of connecting the above junction layers.
After the CMOS semiconductor device has been manufactured by the CMOS fabricating process, a passivation layer for protecting a chip is deposited, and then bonding pads used to connect the CMOS semiconductor device to the lead frame of a package for packaging the CMOS semiconductor using thin metallic wires are formed by etching the passivation layer using a mask.
However, the conventional CMOS fabricating technology requires a packaging process, such as bumping based on wire bonding or ball formation, and a separate mask process adapted to deal with the loss of an area attributable to pads and the formation of pads because semiconductor terminals are always connected to a system via pads.
Furthermore, the conventional technology suffers from difficulty in the configuration of a system due to the three-dimensional (3D) structure of a packaging portion for forming pads, and is problematic in that it is impossible to rapidly measure an unprocessed chip itself when needed.
Moreover, the conventional technology is problematic in that it is difficult to preserve nano-material on a surface when it is used as a sensor because the conventional technology entails a structure in which chip surfaces are not easily exposed.
Recently, with the development of semiconductor fabricating technology, very small-sized nano-devices have been implemented, and the application fields of semiconductor devices have been considerably diversified. Therefore, there is a growing need for the development of a semiconductor device without pads in some application fields in order to overcome the problems attributable to the formation of pads.